Significant for high performance circuits We can utilize only the intrinsic time borrowing of latches to Latches have the time borrowing property STA tools are mature to handle time borrowing The amount of time borrowing offered by the pulse width is Induce some difficulties on timing closure and functional verification Under flip-flop-like timing analysis, prior works use aggressive time borrowing techniques Various pulse widths, clock skew scheduling, and retiming may Multi-bit pulsed-latches are more power efficient than single-bit pulsed latch.īit Number Normalized power per bit1 1.0002 0.7404 0.6138 0.575 ![]() US patent 6856270 B1, 2005.Venkatraman et al., A robust, fast pulsed flip-flop design, GLSVLSI-08. Pulsed-latch-aware placement for timing-integrity optimization. Multi-bit pulsed latch: hardwired PG and L togetherĬhuang et al. Generic pulsed latch:pulse generator (PG) and latches (L) The pulse distortion and clock skew can be well controlled The PG and latches are placed and hard-wired together in a compact and symmetric form The PG and latches are placed apart Multi-bit pulsed-latches The generic PL structure Pulses can easily be distorted since perform placement and clock networkĬo-synthesis (based on 1 and 5)PL - ISPD'12 minimize # of PGs without consideringĬlock gating6. apply aggressive time borrowing techniques (clock skew scheduling, pulse width allocation, retiming) propose a PL-aware analytical placer,Ĭontrolling pulse distortion by limiting the # of PLs and total WL driven by each PG (no timing consideration) Most of previous works adopt the generic PL structureand flip-flop-like timing analysis Migrate from a FF-based design to a PL-based counterpart to reduce the sequencing overhead Pulsed-latch (PL) A latch synchronized by a pulse clock A PL can be approximated as a fast, low-power, and small FF Promising to reduce power for high performance circuits SNUG, 2010.įlip-flop (FF) The most common form of sequencing elements Two cascaded latches triggered by a clock signal High sequencing overhead in terms of delay, power, area ![]() Using multi-bit flip-flop for clock power saving by DesignCompiler. Large portion of it is consumed by sequencing elements Minimize the sequencing overhead!Ĭhen et al. Novel Pulsed-Latch Replacement Based on Time Borrowing andSpiral ClusteringĬHIH-LONG CHANGIRIS HUI-RU JIANGYU-MING YANGEVAN YU-WEN TSAIAKI SHENG-HUA CHENĬlock power is the major contributor of total chip power consumption
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